1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device and a semiconductor device formed by the process. More particularly, it relates to a process for manufacturing a semiconductor device comprising a memory cell portion and a peripheral circuit portion in which a single sidewall spacer is provided on a gate of a transistor in the memory cell portion and a dual sidewall spacer is provided on a gate of a transistor in the peripheral circuit portion, and a semiconductor device formed by the process.
2. Description of Related Art
In recent years, high integration of semiconductor devices such as ICs and LSIs has been remarkable, and advanced miniaturization techniques are required.
For example, in MOS devices which have been used for various applications such as semiconductor memories, a plurality of gate electrodes are arranged on one well, so that space between the gate electrodes has been reduced smaller and smaller as the semiconductor devices have been miniaturized.
In such a semiconductor device, hot carriers are generated by a high electric field and penetrate into a gate oxide film of the semiconductor device, which deteriorates transistor characteristics. To prevent the deterioration caused by the hot carriers, has been proposed a method for providing sidewalls on the sides of a polysilicon gate on the gate oxide film and forming an LDD (Lightly Doped Drain) structure in the neighborhood of a drain below the sidewalls to alleviate the electric field in this region.
Among the semiconductor memories, non-volatile flash memories are capable of writing and reading at any time.
The flash memory is constituted of transistors formed both in a memory cell portion and in a peripheral circuit portion on a p-type silicon substrate 1 as shown in FIG. 3(a) for the memory cell portion and FIG. 3(b) for the peripheral circuit portion. The transistors are connected to a wiring layer formed thereon through contact plugs.
In this flash memory, data writing is performed by applying a high electric field to a drain region of an n+ layer 11 and a control gate 7 and injecting electric charges to a floating gate 6 through a tunnel oxide film 5. Data erasing is performed by applying a positive electric field to the n+ layer 11 and a source region of an nxe2x88x92 layer 12 and applying a negative electric field to the control gate 7 so that the electric charges are drawn to the source region.
In non-volatile semiconductor memory devices such as the flash memories, the memory cell portion has to be highly integrated and miniaturized, while the transistor of the peripheral circuit portion must satisfy a strict requirement in dielectric strength.
Typically, in the above semiconductor devices, the transistors in the peripheral circuit portion and in the memory cell portion are formed simultaneously with a view to simplifying the manufacturing process. Accordingly, sidewalls for the gates of the transistors are also formed in one operation. The sidewalls of the transistor in the peripheral circuit portion are formed thick to meet the strict dielectric strength requirement, and therefore the sidewalls of the transistor in the memory cell portion are also thickened.
However, where the device is integrated higher and the space between the gates becomes narrower, the thick sidewalls on the gate of the transistor in the memory cell portion make it difficult to connect the contact plug to the source/drain region as shown in FIG. 3(a). Therefore, there have been demanded, not only the miniaturization and the high integration of the semiconductor devices, but also secure connection between the contact plug and the source/drain region.
The present invention has been achieved to solve the above drawbacks, and intended to provide a process for manufacturing a semiconductor device which allows thinner sidewalls on the transistor in the memory cell portion as compared with the sidewalls of the transistor in the peripheral circuit portion is required to exhibit the strict insulation resistance, and a semiconductor device formed by the process.
According to the present invention, provided is a process for manufacturing a semiconductor device including a plurality of transistors in each of a memory cell portion and a peripheral circuit portion formed on the same semiconductor substrate, comprising: (a) forming gates of transistors in a peripheral circuit portion; (b) forming first sidewall spacers on sides of the gates; (c) forming gates of transistors in a memory cell portion; (d) forming second sidewall spacers on sides of the gates in the peripheral circuit portion and the memory cell portion, so that singl sidewall spacers are formed on the transistors in the memory cell portion and dual sidewall spacers are formed on the transistors in the peripheral circuit portion; and (e) forming source/drain regions in the peripheral circuit portion and the memory cell portion to obtain a plurality of transistors.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.